Future University In Egypt (FUE)
Future University is one of most promising private universities in Egypt. Through excellence in teaching, research and service, Future University strives to provide a comprehensive, high-quality education that prepares our graduates to be future leaders.
mainLogo
Altagamoa Al Khames, Main centre of town, end of 90th Street
New Cairo
Egypt
Faculty of Engineering & Technology

AHMED SAEED ABDELSAMEA SAYED

Basic information

Name : AHMED SAEED ABDELSAMEA SAYED
Title: Assistant Professor
Google Schoolar Link
Personal Info: Ahmed Saeed obtained his PhD in Electrical Engineering "Electronics and Communication" from Ainshams University and, during his work toward PhD, he was a visiting researcher at System and Architecture Lab in Faculty of Engineering, University of Porto, Portugal. He obtained his BSc and MSc in Communications and Electronics Engineering from Faculty of Engineering, Helwan University, Egypt in 2004 and 2010, respectively, where he was the second of his class. From 2004 to 2016 he was Teaching Assistant in the Electrical Engineering department. Currently, he is an assistant professor in Electrical Engineering Department, Future University in Egypt. In April 2016, Ahmed was visiting staff at Faculty of Engineering, University of Porto, Portugal. In 2018, Ahmed was visiting staff at the School of Engineering, University of Central Lancashire, United Kingdom. He is also a Trainer, Editor,and Digital system designer. Ahmed Assisted and supervised a lot of graduation/commercial projects in the field of IoT, signal processing, communication systems implementation, and digital system design. He is a member in the organization/steering committee for the scientific meetings and events held in Faculty of Engineering. His research interests include low-power implementation of signal processing functions and wired/wireless communication systems on FPGA and ASIC, signal analysis and modeling in high-speed interconnects and Signal Integrity. Ahmed is a member in IEEE and Egyptian Syndicate of Engineers. He published some papers in efficient implementation of the DSP blocks on an FPGA and signal integrity. View More...

Education

Certificate Major University Year
PhD Electronics Engineering Ain Shams University- Faculty Of Engineering 2017
Masters Electronics Engineering Helwan University - Faculty Of Engineering 2010
Bachelor Electronics and Communication Engineering Helwan - Egypt 2004

Teaching Experience

Name of Organization Position From Date To Date
University of Central Lancashire Visiting Staff 01/01/2018 01/01/2018
FUE Assistant Professor 01/01/2017 01/01/2017
Departamento de Engenharia Eletrotécnica e de Computadores / Faculdade de Engenharia, Universidade do Porto Visiting Staff 01/01/2016 01/01/2016
Many Training Company trainer 01/01/2005 01/01/2012
Modern University Teaching Assistant 01/01/2005 01/01/2007

Researches /Publications

A Comparative Study Between Modified MPPT Algorithms Using Different Types of Solar Cells - 01/0

AHMED SAEED ABDELSAMEA SAYED

Doaa Khodair; Ahmed Shaker; Hossam E. Abd El Munim; Mohamed Abouelatta

01/09/2020

The I-V characteristics of the solar cells depend on solar irradiance, shading and temperature, which impact the maximum power point (MPP). This paper presents a comprehensive comparative study between the performance of four MPP tracking (MPPT) algorithms: the Modified Variable Step Size Perturb and Observe (M-VSS-P&O) and Modified Variable Step Size Incremental Conductance (M-VSS-INC) and the conventional P&O and INC. Simulations carried out using Matlab-Simulink to investigate the performance of the two solar cells under STC conditions and in a sudden change in solar irradiance. The simulation results, in both cases, reveal that the modified algorithms could make a correct decision in tracking the MPP and hence achieve better performance regarding the response time and the steady-state power oscillation than the conventional algorithms.

Download PDF
High Efficiency Tandem Perovskite/CIGS Solar Cell - 01/0

AHMED SAEED ABDELSAMEA SAYED

Fathy Z. Amer; Roaa I. Mubarak

01/09/2020

This paper presents a study of a tandem Perovskite/CIGS cell, its performance parameters, and the effect of temperature variations on these parameters. The variation of each sub-cell short-circuit current density value with absorption thickness of perovskite (top) sub-cell has been done to find the matching point, as the two sub-cells equivalent to two series cells. The combining of two sub-cells shows the ability to absorb photons spectrum up to 1120 nm and perform a conversion efficiency about 30.5% (at room temperature) higher than each sub-cell. The variation of temperature from 260 K up to 360 K shows that the power conversion efficiency decreases almost linearly from 33.5% to 26.6%. The validity of the proposed tandem cell is proved by comparing its results with the recent published results. The proposed tandem cell shows one of the highest power conversion efficiency relative to the recent published results.

Download PDF
Thirteen-Level Modified Packed U-Cell Multilevel Inverter for Renewable-Energy Applications - 01/0

AHMED SAEED ABDELSAMEA SAYED

Marwa S. Salem; Ahmed Shaker; Mohamed Abouelatta

01/09/2020

Multilevel inverters are getting more interest to be used in several applications due to their various advantages compared to the classical inverters. In this paper, a modified packed U-cell inverter is proposed to provide thirteen-level smooth waveform at the output. The proposed inverter uses eight switches and three DC sources, which is very less compared to the classical inverters. The efficient multi-carrier PWM switching technique is employed to control the operation of the inverter and to reduce the current harmonics. Simulations are carried out using Matlab/Simulink package to investigate the performance of the proposed inverter. The improvement in the output waveform and the reduced harmonic distortion are pointed out, which prove the efficiency of the proposed inverter.

Download PDF
Implementation of a Low-power Embedded Processor for IoT Applications and Wearables - 01/1

AHMED SAEED ABDELSAMEA SAYED

Kareem Mansour

01/10/2019

—Embedded processors are key building blocks for IoT platforms. Such processors should provide flexible computing and low-power consumption for the small form factor devices to have better battery life. This paper introduces an implementation of a new design for a 32-bit RISC embedded processor optimized for lowpower budget and targeting IoT applications. The proposed processor is capable to execute a small set of simple instructions in few cycles, and hence, efficient for low-power embedded applications. The instruction set is inspired by the state-of-the-art Thumb-2 ISA by ARM. The performance of the processor is analyzed in terms of delay and power. The design is described in VHDL, implemented and simulated on Vivado and tested using Nexys 4 DDR board featuring Xilinx’s Artix-7 FPGA.

Download PDF
A comprehensive simulation study of hybrid halide perovskite solar cell with copper oxide as HTM - 01/1

AHMED SAEED ABDELSAMEA SAYED

Mohamed Abouelatta, Ahmed Shaker

01/10/2019

Perovskite solar cells (PSCs) have attracted considerable attention as a competitor technology in solar cells due to the rapid enhancement in their power conversion efficiency (PCE) in recent years. PSCs have several advantages such as their bandgap tunability, lower cost, tolerance of high impurities, protracted diffusion length and wide optical absorption. In this paper, simulation of PSCs with copper oxide as a hole transport material (HTM) and different electron transport materials (ETMs) has been presented. The proposed materials are a replacement to the ordinary hole and ETMs; such as the titanium dioxide and the expensive spiro-OMeTAD. In addition, a comprehensive study for optimizing the features and parameters of the PSCs, such as the thickness and defect density of the perovskite layer, the doping concentrations, and the bandgap energy, has been introduced. The simulation and the performance evaluation of the designed PSCs have been carried out using SCAPS-1D. The results show that mixed halide PSC with zinc oxysulfide as ETM and copper oxide as HTM has an enhanced performance with a PCE of up to 30.82%.

Download PDF
Implementation of Low-Power Multiply-Accumulate (MAC) Unit for IoT Processors - 01/1

AHMED SAEED ABDELSAMEA SAYED

Kareem Mansour

01/12/2018

Embedded processors are key building blocks for IoT platforms. Multiply-Accumulate (MAC) units are vital arithmetic circuits in several applications performed by the processors including digital signal processing (DSP). It is necessary to reduce the power consumed by the processor. In this paper, the design and implementation of 32-bit MAC unit optimized for low-power budget targeting IoT processors is introduced. The proposed MAC unit is capable of performing several 16bit, dual 16-bit, and 32-bit MAC operations that can be carried out on signed and unsigned numbers with up to three operands involved. The performance of MAC unit is analyzed in terms of delay and power. The unit is described in VHDL, implemented and simulated on Vivado and tested using Nexys 4 DDR board featuring Xilinx's Artix-7 FPGA.

Download PDF
Quantitative Characterization of Clock Signals in the Frequency Domain for Signal Integrity Analysis - 01/0

AHMED SAEED ABDELSAMEA SAYED

Alaa E. El-Rouby ; Y. Ismail ; H. Ragai

01/01/2017

Signal integrity analysis is usually performed solely in the time domain. The traditional way to include the frequency-dependent elements, like interconnects, is to convolve their impulse response with the input and the other circuit element models to obtain the overall response. This method is inefficient in terms of speed of computation and might lead to stability problems. Therefore, transforming all the specifications of system and signals defined in the time domain to the frequency domain and performing a complete frequency-domain based signal integrity analysis, would simplify and speed up the process and make it effectual. In this paper, the relationship between clock signal deviations in the time domain -for example the undershoot, overshoot, and rise and fall times- and their frequency-domain features was quantified, both numerically and analytically. The proposed models are modeled and simulated in Matlab; whereas a point-to-point communication model is built on Keysight's Advanced Design System to justify these models.

Download PDF
Implementation of Fast Discrete Wavelet Transform for Vibration Analysis on an FPGA - 01/0

AHMED SAEED ABDELSAMEA SAYED

Hani Ragai

01/01/2012

The wavelet transform is very important algorithm in signal processing. By using this technique, time-frequency information can be used for analyzing all signals. This paper explains the realization of discrete wavelet transform (DWT) processor for analyzing the vibration signal. The implementation was made on a Field Programmable Gate Array (FPGA) because it can achieve higher computing speed than digital signal processors (DSPs), and also can achieve cost effectively ASIC-like performance with lower development time, and risks. The processor has been developed using hardware description language VHDL and simulated on an Altera Cyclone-IV EP4CE22F17C6N chip.

Download PDF
FPGA implementation of Radix-22 Pipelined FFT Processor - 01/0

AHMED SAEED ABDELSAMEA SAYED

Mohamed E. Elbably, Gamal Abd-Elfadeel, Mohamed I. Eladawy

01/01/2009

The Fast Fourier Transform (FFT) is very important algorithm in signal processing, softwaredefined radio, and wireless communication. This paper explains the realization of radix-2 2 single-path delay feedback pipelined FFT processor. This architecture has the same multiplicative complexity as radix-4 algorithm, but retains the simple butterfly structure of radix-2 algorithm. The implementation was made on a Field Programmable Gate Array (FPGA) because it can achieve higher computing speed than digital signal processors (DSPs), and also can achieve cost effectively ASIC-like performance with lower development time, and risks. The processor has been developed using hardware description language VHDL and simulated up to 465 MHz on an Xilinx xc5vsx35t for transformation length 256-point.

Download PDF
Efficient FPGA implementation of FFT/IFFT Processor - 01/0

AHMED SAEED ABDELSAMEA SAYED

M. Elbably, G. Abdelfadeel, and M. I. Eladawy

01/01/2009

—The Fast Fourier Transform (FFT) and its inverse (IFFT) are very important algorithms in signal processing, software-defined radio, and the most promising modulation technique; Orthogonal Frequency Division Multiplexing (OFDM). This paper explains the implementation of radix-2 2 single-path delay feedback pipelined FFT/IFFT processor. This attractive architecture has the same multiplicative complexity as radix-4 algorithm, but retains the simple butterfly structure of radix-2 algorithm. The implementation was made on a Field Programmable Gate Array (FPGA) because it can achieve higher computing speed than digital signal processors, and also can achieve cost effectively ASIC-like performance with lower development time, and risks. The processor has been developed using hardware description language VHDL on an Xilinx xc5vsx35t and simulated up to 465MHz and exhibited execution time of 0.135μS for transformation length 256-point. This results show that the processor achieves higher throughput and lower area and latency.

Download PDF

Awards

Award Donor Date
IEEE Xplore® Challenge for Researchers IEEE 2018
Outstanding Assistant Lecturer Award Future University in Egypt 2016
Academic Staff, MOBILE + project, in the framework of the European Programme Erasmus+ Departamento de Engenharia Eletrotécnica e de Computadores / Faculdade de Engenharia. Universidade do Porto 2016
PhD Mobility Universidade do Porto 2014
FUE Award to encourage scientific research Future University in Egypt 2011

Follow us on

Visit the Faculty

ADS