Future University In Egypt (FUE)
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Altagamoa Al Khames, Main centre of town, end of 90th Street
New Cairo
Egypt
Faculty of Engineering & Technology
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Mohamed Hassan Elmahlawy

Basic information

Name : Mohamed Hassan Elmahlawy
Title: Associate Professor
Google Schoolar Link
Personal Info: Associate Professor of Electronics, Faculty of Engineering & Technology, Future University in Egypt Design for testability of electronic circuits

Education

Certificate Major University Year
PhD Electrical Engineering - Electronics University of Kent- Faculty Of Engineering - Canterbury - United Kingdom 2002
Masters Electrical Engineering Military Technical College 1995
Bachelor Electrical Engineering Military Technical College 1989

Researches /Publications

Brain Tumor Image Segmentation Based on Deep Residual Networks (ResNets) - 01/0

Mohamed Hassan Mohamed Elmahlawy

Safa Gasser, O. M. Fahmy

01/06/2020

Automatic segmentation of brain tumor from Magnetic Resonance Images (MRI) is one of the challenging tasks in computer vision. Many proposals investigate the use of Deep Neural Networks (DNN) in image segmentation as they have a high performance in automatic segmentation of brain tumors images. Due to the gradient diffusion problem and complexity, it generally takes a lot of time and extra computational power for training deeper neural networks. In this paper, we present an automatic technique for brain tumor segmentation depending on Deep Residual Learning Network (ResNet) to get over the gradient problem of DNN. ResNets accomplish more accuracy and can make the training process faster compared to their equivalent DNN. To achieve this enhancement, ResNets add a shortcut skip connection parallel to convolutional neural networks layers. Simulation examples have been carried out on dataset BRATS 2015 to verify the superiority of the proposed technique. Results verify that the proposed technique has an improved accuracy of 83%, 90%, and 85% for the complete, core, and enhancing regions, respectively. Moreover, it has an average computation time (3 times) faster than other DNN techniques.

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Remote Fault Diagnosis for Testing Digital Circuits through Internet of Things in Industrial Applications - 01/1

Mohamed Hassan Mohamed Elmahlawy

Ahmed Mosad Mohamed

01/12/2019

In this paper, the new remote edge fault diagnosis method for testing digital circuits is presented. The proposed test system generates the target test patterns to the circuit under test (CUT), receives test responses from the CUT for signature compaction generation, and carries out the edge fault diagnosis algorithm through the Internet of Things (IoT) between the main repair workshop and the small repair workshop. The edge fault location enables to locate faults in all edges of the printed circuit board (PCB) to the edge level not the nodal level. In addition, the merge between the edge fault diagnosis and the IoT enables to integrate the huge testing capabilities of the main repair workshop to the small repair workshop. This method consists of three main phases; fault detection phase, fault location phase, and remote testing using the IoT phase. It is applied to test some digital circuits and compared with the previously published related testing methods. The experimental results show that this method is effective in terms of fault coverage, the portability, hardware overhead, and remote testing.

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Parametric Fault Detection of Analogue Circuits Based on Optimized Support Vector Machine Classifier - 01/1

Mohamed Hassan Mohamed Elmahlawy

Hossam E. Abou-Bakr Hassan

01/12/2018

Parametric faults in analogue circuits cause system performance degeneration and are hard to be detected. There are no clear boundaries between fault-free and faulty circuit output due to components tolerances. Therefore, a machine learning classifier needs to be learned to correctly classify circuit outputs. In this paper, the parametric fault detection method of analogue circuits based on the support vector machine (SVM) classifier is developed. The proper choice of kernel parameters for the SVM in the training process improves the classification accuracy. The penalty parameter and kernel function parameters for the radial basis function (RBF) kernel should be optimized. In addition, the Bayesian optimization methodology is used to select the hyperparameters for the SVM classifier. The Biquad filter, one of the benchmark circuits, is utilized to validate the proposed method and compare it with the other methods. Using downside minimum size detectable fault (DMSDF) and upside minimum size detectable fault (UMSDF) values, the method gives good enhancements in detecting faults due to minor changes in components values above or down the nominal component values.

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New Hybrid-Based Self-Test Strategy for Faulty Modules of Complex Microcontroller Systems - 01/1

Mohamed Hassan Mohamed Elmahlawy

Sherif Hussein, and Gouda I. Moham

01/12/2018

have become a widely accepted architecture for highly complex embedded systems on a single chip (SoC). It consists of deeply embedded heterogeneous components with poor accessibility makes their testing process a difficult task using hardware based self-test (HBST). Software-based self-test (SBST) is considered to be a promising testing technology for these systems. Almost every SoC contains at least one embedded processor, SBST utilize this processor for test pattern generation (TPG) and test response compaction (TRC) based on its instruction set, then test response will be unloaded and evaluated using external automatic test equipment (ATE). In this paper, SBST strategy disadvantages in microcontroller testing will be identified. Then, a new testing approach that combines both the HBST and the SBST, called hybrid-based self-test (HYBST) will be introduced. Based on a divide-and-conquer approach, HYBST identify microcontroller's components and their corresponding component operations. Feasibility and effectiveness of HYBST and SBST methodologies will be assessed by applying them to a Microchip ® PIC16F877A and PIC18F452 in terms of memory usage, time consumption and number of tested modules found in microcontrollers.

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Test Pattern Generator Optimization for Digital Testing of Analogue Circuits - 01/1

Mohamed Hassan Mohamed Elmahlawy

Aiman Mousa

01/12/2017

In this paper, the proposed design for digital testing of analogue circuits (DTAC) is presented. The proper selection of the analogue test pattern generator (ATPG) for stimulating and detecting faults is the target issue. Component tolerance of the analogue circuit under test produces signature boundaries in the analogue test response compactor. Signature boundary difference (SBD) is determined for different ATPGs. The minimization of the SBD increases the differentiation between the faulty and golden cases. Each part of the DTAC is modeled and evaluated to select the proper ATPG such that the SBD is minimized. Based on the experimental results of some analogue benchmark circuits, the best ATPG for detecting faults is selected based on the minimal SBD. Different ATPGs may change from a circuit to another one. These results are contrary to the previous published work that selected the pulse waveform as the best ATPG because of its superiority in terms of power spectral density.

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Efficient Microcontroller System to Test an SRAM Chip Using Signature Analysis - 01/1

Mohamed Hassan Mohamed Elmahlawy

Mahmoud S. Ragab ; Emad A. El-Samahy

01/12/2017

Memory in recent technology is considered an important element in the electronic system. It is required to test the memory for high fault coverage and less test application time. In this paper, the low-cost design of the microcomputer-based testing (MBT) for the static random access memory (SRAM) is presented using signature analysis. The memory test pattern generator (MTPG), the test response compaction based on the signature analysis, the memory under test (MUT), and the memory test controller are considered the main parts of the MBT. The proper selection of the MTPG for stimulating and detecting faults is the target issue. In this paper, all March tests that detect memory faults are considered. The combination of March tests is selected to select the proper MTPG and to detect all current faults of the MUT. Using UD- and LSD March tests with test sequence length, 87n, all possible current memory faults based the MBT are detected.

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Efficient Computerized-Tomography Reconstruction Using Low-Cost FPGA-DSP Chip - 01/0

Mohamed Hassan Mohamed Elmahlawy

Bassam A. Abo-Elftooh, and Mahmoud E. A. Gadallah

01/06/2017

In this paper, filtered back-projection algorithm is optimally implemented using low-cost Spartan 3A-DSP 3400 chip. The optimization enables parallel implementation. The combination of the pixel parallelism and projection parallelism is presented to significantly reduce the total reconstruction time to produce the image. The applied data is presented in fixed point format to achieve efficient implementation with maximum speed. The selection of data bus-width is optimized with very little error and good visual quality required for medical images. Before implementation, the computer tomography (CT) reconstruction simulator is developed to provide a testing reference for the hardware implementation. Using the combination of the pixel parallelism and projection parallelism, the presented hardware design achieves image reconstruction of a 512-by-512 pixel image from 1024 projections in 134.8 ms using 50 MHz clock cycles. It achieves the reduction of the required number of clock cycles to form an image from projections by 60 % comparing to the state of the art of the reconstruction time using field programmable gate array (FPGA) design.

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Digital Signature Based Test of Analogue Circuits Using Amplitude Modulated Multi-Tone Signals - 01/1

Mohamed Hassan Mohamed Elmahlawy

Mohamed S. Saleh ; Hossam E. Abou-Bakr Hassan

01/12/2016

In this paper, a new multi-tone test method for fault detection of analogue circuits is presented. This method determines all applicable frequencies of the test set that is ranked, and then compacted using the digital signature. The experimental results show that this method is effective over previous published related testing methods in the fault simulation count and the application test time. Instead of testing the analogue circuit under test (ACUT) at each applicable frequency in the test set, a multi-tone test signal is composed of all applicable frequencies in a single test signal. The attenuation of the amplitude component of some applicable frequencies due to passing through analogue filters reduces the fault detection of the test set. Therefore, it is solved by applying the amplitude modulated multi-tone signal. The experimental results illustrate that the modulated multi-tone signal is better for the early fault detection which leads to better detection of parametric faults of the ACUT.

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Two-Test Pattern Capabilities of the LFSR/SR Generator in Pseudo-Exhaustive Testing based on Coding Theory Principles - 01/0

Mohamed Hassan Mohamed Elmahlawy

Emad H. Khalil, Fawzy Ibrahim, and Mohamed. H. Abd El-Azeem

01/07/2016

Testing of digital integrated circuits for delay and CMOS stuck-open faults requires two-test patterns. Built-in self-test (BIST) schemes are required to comprehensive testing of such faults. BIST test pattern generators for two-test pattern should be designed to ensure high transition coverage. The test pattern generator (TPG) circuits treated here are not limited to linear feedback shift registers (LFSRs) but include the linear feedback shift register / shift register (LFSR/SR) circuits. It is required to increase the number of each subset of the state variables for complete transition coverage based on the optimal test lengths. In this paper, the two-test pattern capabilities of the LFSR/SRs are explored using transition coverage as the metric. The necessary and sufficient conditions to ensure complete transition coverage for LFSR/SRs are derived. The theory, developed here, identifies all LFSR/SRs as the TPGs that determine the complete transition coverage under any size constraint. It is shown that the testing of digital integrated circuits based on the LFSRs with primitive polynomials with large number of terms is better in the case of the two-test patterns. Based on the necessary and sufficient conditions, the two-test pattern testing is developed using the procedures outlined in this paper to get high robust path delay fault coverage with the optimal shortest test lengths.

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New Testability Analysis and Multi-Frequency Test Set Compaction Method for Analogue Circuits - 01/0

Mohamed Hassan Mohamed Elmahlawy

Mohamed S. Saleh ; Hossam E. Abou-Bakr Hassan

01/06/2016

In this paper, the new testability analysis method of analogue circuits is presented. The observability of parametric faults is evaluated by determining a proper test signal that maximizes the error between the good and the faulty circuit at a target fault. The efficient method to optimize the multi-frequency test set by determining the basis of the decision matrix is presented. The decision matrix is calculated from the frequency set of the test signal, extracted from the testability analysis. This set is ranked by calculating the total fault coverage of each test signal. The analog test problem is formulated as selecting an optimal subset from an initial test set defined in terms of fault coverage and fault separation on a given fault set. The presented method is applied to test some analogue benchmark circuits [1] and compared with previous published testing methods. The results show the superiority of our presented method.

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Signature-Based Self-Test Approach for Single-Shot Circuits on the Circuit Board Level - 01/0

Mohamed Hassan Mohamed Elmahlawy

01/06/2016

Several literatures focused on self-testing of digital and analog integrated circuits. They proposed different test scenarios for the circuit board based on the signature analysis. The single-shot (SS) circuit is important element on the circuit board level in the industrial applications. In this paper, a new testing design is presented to functionally test the SS circuit on the circuit board. It can test the SS circuit by measuring the time duration based on the edge detecting of the stimulated pulse. This time duration is considered the signature of its proper functionality. Two testing designs are proposed. Different pulse durations with different rising and falling time are applied to the proposed testing design. The experimental results illustrate the efficiency of the presented testing design in both the millisecond range and the microsecond range.

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New Algorithm to Segment Combinational Circuits in Pseudo-Exhaustive Testing - 01/0

Mohamed Hassan Mohamed Elmahlawy

Winston Waller

01/06/2016

In pseudo-exhaustive testing, the circuit is segmented into m output cones, and each out¬put cone is exhaustively tested. The test ensures detection of all detectable faults within the individual output cones of the circuit without the need for the fault simula¬tion. The use of pseudo-exhaustive testing is associated with certain costs. It includes the hardware cost of inserting segmentation cells to segment the circuit. In this paper, a new algorithm to segment combinational circuits is presented to reduce the hardware cost of inserting segmentation cells. In this algorithm, several heuristic procedures are proposed to handle different circuit topologies. The concept of limited global effect is presented. The limited global effect is to study the effect of a candidate node with respect to a particular subset of the nodes in its fan-out cone (FOC). Several approaches for the selection of the candidate nodes are presented, also. The experimental results for all combinational ISCAS85 benchmark circuits (F. Brglez, 1985) indicate the superiority of the presented algorithm in this paper with respect to all previous published algo¬rithms. Using the presented algorithm, no deviation of the number of segmentation cells from the expected behav¬iour for all cone size reduction values of all combinational ISCAS85 benchmark circuits between 16 to 32 is achieved - another improvement over previously published algorithms.

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FPGA-Based Implementation of the Digital Testing of Analogue Circuits - 01/0

Mohamed Hassan Mohamed Elmahlawy

Sherif Anis, Mahmoud E. A. Gadallah, and Emad A. El-Samahy

01/04/2016

This paper presents a new parametric fault detection testing approach for analogue circuits, based on digital testing. The design and implementation is achieved using the field programmable gate array (FPGA) as the digital part besides the analogue part that includes the analogue conditioning and the data acquisition circuitry. The analogue test pattern generator (ATPG) is designed to sweep frequencies of the sinusoidal waveform to match the frequency domain of the analogue circuit under test (ACUT). The binary generation of the ATPG can be viewed as variable delay samples of the swept sinusoidal signal. The analogue test response compactor (ATRC) is designed based on sample accumulation of the test response to generate a digital signature. The test controller is designed to enable the proper synchronization of the analogue test cycle for stable digital signature generation. The signature comparison is achieved based on signature boundary of the worst-case analysis. In addition, the deduced signature combines effective parameters of the transfer function of the ACUT with respect to the component variations. These parameters are the bandwidth (BW) and the pass-band transmission (Amax). Then, the signature curve of each component variations in the ACUT is used for the ACUT judgment. The presented analogue testing is applied to the ACUT, selected from the analogue benchmark circuits in the frequency range of biomedical applications.

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New Test Pattern Generators for the BIST Pseudo-Exhaustive Testing based on Coding Theory Principles - 01/0

Mohamed Hassan Mohamed Elmahlawy

Winston Waller

01/04/2016

In this paper, an efficient algorithm to design convolved LFSR/SR (Linear Feedback Shift Register / Shift Register) for the pseudo-exhaustive testing (PET) is presented as far as the lengths of the test set and hardware overhead are concerning. In this algorithm, an efficient search to reduce the constraint in the size of the shift register (SR) segment and makes an effi¬cient search to restrict on the number of feed forward stages into two stages at most and no restriction on the size of the SR segment. The residues are assigned such that minimum hardware overhead is achieved. This search generates several possible solutions for each case, from which the minimal hardware solutions may be chosen. In addition, a new test pattern generator (TPG) for the PET that bridges the gap between convolved LFSR/SR and permuted LFSR/SR is presented. It is considered to be the opti¬mal pseudo-exhaustive test pattern generator (PETPG) as far as the lengths of the test set and hardware overhead are concerning. An efficient residue assignment for the in¬puts of the CUT to reduce the hardware overhead is presented. With small number of permutations in the assigned residues, the chance of obtaining efficient solutions may be increased. The presented generator in this paper is considered the general form of the PETPG. The simple LFSR/SR, the permuted LFSR/SR, and convolved LFSR/SR are considered the special case. The experimental results for all combinational benchmark circuits [1] indicate the superiority of the presented approach with respect to previous published works.

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Signature Multi-Mode Hardware-Based Self-Test Architecture for Digital Integrated Circuits - 01/1

Mohamed Hassan Mohamed Elmahlawy

01/12/2015

In this paper, the new signature multi-mode hardware-based self-test architecture (SM-HBST) for digital integrated circuits (ICs) is presented for fault diagnosis. It generates test patterns either pseudo-randomly, or deterministically to test the random logic. Also, it generates efficient test patterns to test the static random access memory (SRAM) based on March testing approach. The response of the circuit is evaluated by the test response compactor (TRC). The proper timing between the test pattern generator (TPG), the circuit under test (CUT), and the TRC is achieved to control the test cycle for stable signature generation. In addition, this architecture can test the single-shot (SS) circuit by measuring the time duration based on the edge detecting of the generated pulse. This time duration is considered the signature of its proper functionality. The SM-HBST is design and implemented based on the Field Programmable Gate Array (FPGA) technology. The experimental results illustrate the efficiency of the SM-HBST as the integrated test solution for fault diagnosis of the digital circuit boards.

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Design and Development of a Low Cost Prosthetic Arm Control System Based On sEMG Signal - 01/1

Mohamed Hassan Mohamed Elmahlawy

Ahmed M. Azab, Ahmed Onsy

01/11/2015

Many human activities depend on upper-limb motion using the activation levels of the electromyography (EMG) signal of the upper-limb muscles during elbow extension and flexion. Different methods are commonly described in the literature, but there are many problems to deal with online processing of the raw EMG such as the speed requirements of real-time applications and memory requirements. The aim of the presented work is to design and develop a low cost prosthetic arm based on the EMG signal activities of the biceps muscle using rectified envelope EMG signal as a control signal. This paper focuses on the development and validation of the proposed low-cost control system during upper limb activities. This validation is passing through several stages until the generation of the control signal to move the prosthetic arm. The EMG signal is processed, and the relationship between elbow motion and the activity level of the biceps muscle is characterized using relevant extracted features (RMS). The validation of the new low-cost system is compared to the Bioback MP150 specialized system based on the envelope of the EMG signal and the raw EMG signal. The experimental results illustrate that the envelope of the EMG signal has the same features-print as the raw EMG signal, and finally the envelope of the EMG signal can generate the control signal to move the prosthetic arm.

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Low-Power Low-Noise CTIA Readout Integrated Circuit Design for Thermal Imaging Applications - 01/0

Mohamed Hassan Mohamed Elmahlawy

Mohmed Raffat, Ahmad Hafez, and Mahmoud S. Hamed

01/09/2015

This paper targets the design of a high dynamic range low-power, low-noise pixel readout integrated circuit (ROIC) that handles the infrared (IR) detector’s output signal of the uncooled thermal IR camera. Throughout the paper, both the optics and the IR detector modules of the IR camera are modeled using the analogue hardware description language (AHDL) to enable extracting the proper input signal required for the ROIC design. A capacitive trans-impedance amplifier (CTIA) is selected for design as a column level ROIC. The core of the CTIA is designed for minimum power consumption by operation in the sub-threshold region. In addition, a design of correlated double sampling (CDS) technique is applied to the CTIA to minimize the noise and the offset levels. The presented CTIA design achieves a power consumption of 5.2μW and root mean square (RMS) output noise of 6.9μV. All the circuits were implemented in 0.13µm CMOS process technology. The design rule check (DRC), layout versus schematic (LVS), parasitic extraction (PE), Process-voltage-temperature (PVT) analysis and post-layout simulation are performed for all designed circuits. The post-layout simulation results illustrate enhancement of the power consumption and noise performance compared to other published ROIC designs. Finally, a new widening dynamic range (WDR) technique is applied to the CTIA with the CDS circuit designs to increase the dynamic range (DR).

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Monitoring of Upper-Limb EMG Signal Activities Using a Low Cost System: Towards a Power-Assist Robotic Arm - 01/0

Mohamed Hassan Mohamed Elmahlawy

Ahmed M.Azab, and Ahmed Onsy

01/07/2015

Many human activities depend on upper-limb motion, which can be characterized and estimated using the activation levels of the electromyography (EMG) signal of the upper-limb muscles. Researchers are devoting much effort to investigating these activities during elbow extension and flexion. Also, a few studies have concluded with the development of a power-assisted arm. However, the systems introduced so far are expensive and there are long waiting lists of people requesting such systems. The aim of the present work is to develop a power-assist arm based on the EMG signal activities of the upper-limb, and this paper describes the first part of this study focusing on the monitoring of EMG signals during upper limb activities based on the development of a low-cost system. The relationship between elbow motion and the activity level of the biceps muscle is characterised and different relevant features are logged. The new low-cost system is then validated against the Biopack specialised biomedical measurement system.

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New Digital Testing of Analogue Circuits - 01/0

Mohamed Hassan Mohamed Elmahlawy

Sherif Anis, Mahmoud E. A. Gadallah, and Emad A. El-Samahy

01/05/2015

This paper presents a new parametric fault detection approach for analogue circuits based on the digital signature analysis. This approach has two main parts, an analogue test pattern generator (ATPG), and an analogue test response compactor (ATRC). The proper ATPG is designed to sweep the applying sinusoidal frequencies to match the frequency domain of the analogue circuit under test (ACUT). The output test response of the ACUT is acquired via the analogue-to-digital converter (ADC). The ATRC accumulates digital samples of the output response from the ADC to generate a digital signature that can characterize the situation of the ACUT. The signature comparison is achieved based on signature boundaries and the worst-case analysis. In addition, the signature curve for each component variations in the ACUT is presented. It combines effective parameters of the transfer function of the ACUT with respect to the component variations. These parameters are the band-width and the passband transmission. In this paper, the hardware implementation is achieved using the field programmable gate array (FPGA) technology as the digital part and the analogue part that includes the data conversion. The digital test controller is designed to enable the proper control and synchronization of the analogue test cycle for stable digital signature generation. The presented testing approach is applied to the ACUT in the range of biomedical applications to validate it. Based on the presented hardware implementation, the signature curve for each component of the ACUT is derived for the ACUT judgment.

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Monitoring of Upper-Limb EMG Signal Activities Using a Low Cost System; Towards a Power-Assist Robotic Arm - 01/0

Mohamed Hassan Mohamed Elmahlawy

Ahmed M.Azab, Ahmed Onsy

01/05/2015

Many human activities depend on upper-limb motion, which can be characterized and estimated using the activation levels of the electromyography (EMG) signal of the upper-limb muscles. Researchers are devoting much effort to investigating these activities during elbow extension and flexion. Also, a few studies have concluded with the development of a power-assisted arm. However, the systems introduced so far are expensive and there are long waiting lists of people requesting such systems. The aim of the present work is to develop a power-assist arm based on the EMG signal activities of the upper-limb, and this paper describes the first part of this study focusing on the monitoring of EMG signals during upper limb activities based on the development of a low-cost system. The relationship between elbow motion and the activity level of the biceps muscle is characterised using relevant extracted features (RMS and STD). The new low-cost system is then validated against the Biopack specialised biomedical measurement system.

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Parametric Fault Detection of Analogue Circuits - 01/0

Mohamed Hassan Mohamed Elmahlawy

Sherif Anis, Mahmoud E. A. Gadallah, and Emad A. El-Samahy

01/06/2014

This paper presents a new testing approach for analogue circuits based on the digital signature analysis. In this paper, the efficient parametric fault detection approach for analogue circuits using the simulation environment is presented. This approach has three main parts, an analogue test pattern generator (ATPG), an analogue test response compactor (ATRC), and an analogue circuit under test (ACUT) model, build in the PSpice circuit simulator. The proper ATPG is designed to sweep the applying sinusoidal frequencies to match the frequency domain of the ACUT. The output test response of the ACUT is acquired via the analogue-to-digital converter (ADC). The ATRC accumulates digital samples of the output response from the ADC to generate a digital signature that can characterize the situation of the ACUT. The signature comparison is achieved based on signature boundaries based on the worst-case analysis. In addition, the signature curve for each component variations of the ACUT is presented to be illustrated as image of some parameters affected in the transfer function of the ACUT. It combines effective parameters of the transfer function of the ACUT with respect to the component variations. These parameters are the band-with and the passband transmission. Using the signature curve, a parametric fault of each component of the ACUT can be detected under the sweep sinusoidal frequency of the ATPG. The presented testing approach is applied to the analogue benchmark circuit to validate the presented testing approach.

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Hybrid based Self-Test Solution for Embedded System on Chip - 01/1

Mohamed Hassan Mohamed Elmahlawy

Sherif I. Morsy, and Gouda I. Mohamed

01/12/2013

Microcontrollers have become a widely accepted architecture for highly complex embedded systems on a single chip (SoC). It consists of deeply embedded heterogeneous components with poor accessibility makes their testing process a difficult task using hardware based self-test (HBST). Software-based self-test (SBST) is considered to be a promising testing technology for these systems. Almost every SoC contains at least one embedded processor, SBST utilize this processor for test pattern generation (TPG) and test response compaction (TRC) based on its instruction set, then test response will be unloaded and evaluated using external automatic test equipment (ATE). In this paper, SBST strategy disadvantages in microcontroller testing will be identified. Then, a new testing approach that combines both the HBST and the SBST, called hybrid-based self-test (HYBST) will be introduced. Based on a divide-and-conquer approach, HYBST identify microcontroller's components and their corresponding component operations. Feasibility and effectiveness of HYBST and SBST methodologies will be assessed by applying them to a Microchip® PIC16F877A and PIC18F452 in terms of memory usage, time consumption and number of tested modules found in microcontrollers.

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